1. Field of the Invention
The present invention relates to a method for accessing, in reading, writing and programming, to a monolithically semiconductor-integrated memory electronic device of the Flash EEPROM type with NAND architecture comprising at least one memory matrix organized in rows and columns of memory cells.
2. Description of the Related Art
It is known that the market of non-volatile memories, for example of the EEPROM or Flash EEPROM type, is currently growing and the most promising applications relate to the “data storage” field.
Until recently, the market almost exclusively involved the consumer field of digital cameras, with the support cards or the known USB keys that represent expandable mobile memories for personal computers.
Therefore, the demand for these products by the consumer was mainly addressed to flash memories of large capacity.
This trend appears to continue in the coming years by virtue of newer applications of the portable electronic devices, which require greater memory capacity, for example for digital cameras or for mobile phones of the last generation operating for example according to the standard 3G or UMTS.
For these applications Flash memories having several advantages in terms of low power consumption, quiet operation, reduced space, etc., and would seem to be particularly suitable.
As is known to the skilled person in the art, Flash memory architectures utilize two fundamental structures, the first of which refers to the traditional and widely tested NOR architectures, and the second one is the more innovative and promising NAND architecture.
For the previously cited applications, the flash architecture most suitable for the requirements of low power consumption, high density, and high program and erase speed is that of the NAND type, which handles, in a simple and fast way the largest amounts of “synchronous” data in reading and programming.
Although having the feature of a high data modify speed, such NAND memories do not allow a fast random access to the same since they are designed for entire pages of at least 512 bytes and not of the single bytes.
In fact, the NAND access protocol is quite slow in random access due to the known latency time, and it exhibits serious difficulties for accessing a sector or a page in a random way.
To meet the increasing needs of portable electronic devices, it would be necessary to have in a same memory also an excellent random access time, such as to perform the code or the boot of the operative system or of the programs without the burdensome use of a RAM.
The fact is also to be taken into consideration that the lithographic sizes for the manufacturing of non volatile memories have reached lower limits of about 65 nm, or even of 32 nm, such as not only to make the construction of the interface between the decoding circuitry and the matrix of the cells themselves difficult, but also such as to enormously increase the propagation times of the signals due to the length of the lines.
In this respect, an important role is played by the row decoding circuitry, whose architecture conditions both the size and the time of the memory access. This is particularly true where the row lines reach extreme compactness levels, especially in NAND Flash, and the problem becomes exacerbated and the implementation becomes complex to such an extent as to make the area occupation inefficient.
The programming and erasing operations occur by exploiting the Fowler-Nordheim phenomenon, while the reading is an operation of the dynamic type. Now, also due to this the reading step is slowed substantially.
It is to be remembered that in a sector of the NAND type, the minimal erasing unit consists of a group of word lines equal to the number of cells of the stack included between the lines SSL and DSL intercepting them, i.e., 16 or 32 according to the memory sizes.
This implies that each stack elemental structure has a reduced conductivity, thus being a strong limitation for the reading structure. The conventional stack structure (16, 32 cells) thus exhibits intrinsic slowness since it has low capacity.
In addition, current NAND memories do not carry out an operative code, for example of the XIP type, since the random access time typical of these architectures is on the order of 10-20 usec.
The reasons for this slowness are due to different components of the memory:
a) to the particular organization of the matrix that normally comprises groups of 16/32 cells in series, which greatly decreases the conductivity of each group;
b) to the great number of wirings of the elemental groups along a same bit-line which increases its load, thus resulting in substantial latency;
c) to the NAND protocol which, conventionally, is oriented to the reduction of the terminals and to a sequential management both of the commands and of the data.
The burden of the load due to the bit line BL is greater than in the corresponding NOR-Flash since in the NAND-Flash the generic bit line BL collects the capacities of all the stack structures which, combined with the large capacities of the memory, significantly increase the value thereof.